Non-volatile memory integrated circuit

ABSTRACT

A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

CROSS REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to U.S. ProvisionalApplication Serial No. 60/460,799, filed on Apr. 4, 2003, which isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] a. Technical Field

[0003] The present invention is in the field of non-volatile memoryintegrated circuits.

[0004] b. Description of the Related Art

[0005] Two well known types of non-volatile memory integrated circuitsare: (1) electrically-erasable electrically-programmable read onlymemory (EEPROM) integrated circuits; and (2) electrically flashreprogrammable read only memory (flash) integrated circuits.

[0006] A typical EEPROM includes an array of memory cells, with eachmemory cell consisting of two MOSFET transistors: a select transistorand a storage transistor. The select transistor controls access to thestorage transistor. The storage transistor includes a source region, adrain region, and a channel region between the source and drain regions.Two gates overlie the channel region: (1) a lowermost,electrically-isolated, floating gate; and (2) an overlying, controlgate. A thin oxide layer, called tunnel oxide, is between the floatinggate and the channel region. Electrons move back and forth through thetunnel oxide by Fowler-Nordheim tunneling, leaving the floatinggate-with either a net positive or a net negative charge. When a netpositive charge is on the floating gate, the storage transistor conductswhen a specified read voltages is applied to the control gate. When anet negative charge is on the floating gate, the storage transistor doesnot conduct upon application of the read voltage. The conductive stateis interpreted as a logical one, and the nonconductive state isinterpreted as a logical zero.

[0007] EEPROMs have attributes that make them better for someapplications than others, due to the fact that EEPROMs have separateselect and storage transistors. For instance, EEPROMs are robust andreliable. Moreover, because of the separate select transistor, EEPROMcells may be erased at the byte and page level. EEPROM cells also areefficient users of current, because the programming current is very lowwith Fowler-Nordheim tunneling. On the other hand, EEPROMs arerelatively low speed, and each EEPROM cell occupies a relatively largearea. The large area results from the presence of the two transistors,and the need for each memory cell to have contacts for connecting bothto a bitline and a wordline.

[0008] A flash memory, by contrast to an EEPROM, is comprised of singletransistor memory cells. The flash memory cell includes a lowermost,polysilicon floating gate, and an overlying polysilicon control gate. Athin tunnel oxide layer separates the floating gate from the substrate.Both the programming and erase operations occur through Fowler-Nordheimtunneling of electrons through the tunnel oxide between the floatinggate and the semiconductor substrate.

[0009] Like EEPROMs, flash memory has features that make it better forsome applications than others. For instance, flash memory cells occupymuch less area than EEPROM cells, and are faster. However, flashmemories cannot be erased in as selective a manner as an EEPROM. Flashmemory is erased in blocks. Further, in a flash memory, because there isnot a separate select transistor, an operation directed at one cell caneasily disturb the stored charge on the floating gate of nearby cells.Because of this risk of disturbance, flash memories must include circuitto verify the contents of the memory. This verify circuitry consumescurrent, which can affect the operation time of battery-operateddevices. In addition, while flash cells are much smaller than EEPROMcells, there are contacts at each memory cell to a bitline and awordline, and these contacts consume valuable chip area.

[0010] Clearly, it would be desirable to have a non-volatile memory thatcombines the reliability and low current operation of an EEPROM, whileat the same time having the small size and speed of a flash memory.

SUMMARY OF THE INVENTION

[0011] The present invention includes a non-volatile memory, a memorycell for the non-volatile memory, a method of operating the non-volatilememory, and a method of making the non-volatile memory, amongst otheraspects. As exemplified by the disclosed embodiments, the inventionsubstantially reduces the size of the memory cell relative to EEPROMs,and provides a simple and reliable memory solution for embeddedapplications and serial flash applications, among other possibilities.

[0012] In one embodiment, the non-volatile memory includes rows andcolumns of non-volatile memory cells formed in a first region of a firstconductivity type in a semiconductor substrate. Shallow implant regionsof a second conductivity type are provided in the first region, in theform parallel pairs of lines. One of a plurality of columns of thememory cells overlaps each pair of implant region lines, which functionas local bitlines. One of the diffusion region lines provides respectivesource regions for all of the memory cells of the respective column, andthe other of the diffusion region lines of the pair provides respectivedrain regions for all of the memory cells of the column. Respectivesubportions of the first region between the diffusion region lines ofthe pair (i.e., between the source and drain regions of the respectivememory cells) form the channel region of the memory cell.

[0013] Plural isolation region lines, such as field oxide lines orshallow trench isolation lines, are formed in the first region andextend parallel to the diffusion region lines, with one of therespective isolation region lines separating adjacent pairs of thediffusion region lines. Accordingly, the columns of memory cells areisolated from each other by an intervening one of the isolation regionlines.

[0014] A thin tunnel oxide layer is formed on the source side each ofthe memory cells, over and in contact with the source region of thememory cell. At each of the memory cells, an electrically-isolatedrectangle of polysilicon located over and in contact with the tunneloxide layer serves as a floating gate, which stores positive or negativecharge, depending on whether the memory cell is storing a logical one orzero.

[0015] A second layer of polysilicon is formed into parallel wordlinesthat each extend perpendicularly to the diffusion region lines. Each ofthe polysilicon wordlines overlies a respective one of the rows ofmemory cells. In particular, each polysilicon wordline overlies thefloating gate, the source region, the drain region, and the channelregion of each of the plural memory cells of the particular row ofmemory cells, as well as the isolation region line that is betweenadjacent memory cells of the row. At each of the memory cells of therow, a respective, integral subportion of the polysilicon wordlinefunctions as the control gate of the memory cell. An intervening layerof dielectric material separates the polysilicon wordline from theunderlying floating gate, the channel region, and the drain region ofthe memory cell.

[0016] The exemplary non-volatile memory cells disclosed herein have thereliability and low current consumption of an EEPROM cell, while alsohaving the small area and speed of flash memory. Each memory cellincludes a select transistor in series with a storage cell, as in anEEPROM, but there is only a single source region, drain region, andchannel region, as in a flash memory cell. The number of contacts forthe memory array are drastically reduced in comparison to both EEPROMand flash memory cells. In addition, interaction between adjacent memorycells, in the wordline direction, is suppressed by using separate localbitlines for the cell source and drain regions, and by providing anisolation region between the adjacent cells. Further, the memory cellhas an integrated select gate that avoids the cumbersome verify cyclesneeded by standard flash memory.

[0017] These and other aspects of the present invention will becomeapparent in view of the detailed description and the accompanyingdrawings of the exemplary embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a cross-sectional side view of a first embodiment of anon-volatile memory cell, and portions of two adjacent memory cells,taken along a wordline of a memory array, in accordance with the presentinvention.

[0019]FIG. 2 is a schematic diagram of an array of the non-volatilememory cells of FIG. 1.

[0020]FIG. 2a is a table of parameter values for erase, write, and readoperations of the non-volatile memory cells of FIG. 2.

[0021]FIG. 3 is a schematic diagram of a non-volatile memory arrayshowing an interconnection of plural blocks of the memory cells of FIGS.1 and 2, and parameter values for operation of the memory array.

[0022]FIGS. 4a-4 e are cross-sectional side views of stages in a firstprocess for making memory cells, in accordance with the presentinvention.

[0023]FIGS. 5a-5 d are cross-sectional side views of stages in a secondprocess for making memory cells, in accordance with the presentinvention.

[0024]FIG. 6 is a cross-sectional side view of a second embodiment of anon-volatile memory cell, and portions of two adjacent memory cells,taken along a wordline of a memory array, in accordance with the presentinvention.

[0025]FIG. 7 is a schematic diagram of an array of the non-volatilememory cells of FIG. 6.

[0026]FIG. 7a is a table of parameter values for erase, write, and readoperations of the non-volatile memory cells of FIG. 7.

[0027]FIG. 8 is a schematic diagram of a non-volatile memory arrayshowing an interconnection of plural blocks of the memory cells of FIGS.6 and 7, and parameter values for operation of the memory array.

[0028]FIGS. 9a-9 e are cross-sectional side views of stages in a firstprocess for making memory cells, in accordance with the presentinvention.

[0029]FIGS. 10a-10 d are cross-sectional side views of stages in asecond process for making memory cells, in accordance with the presentinvention.

[0030] In the drawings of the exemplary embodiments, like features arelabeled with the same reference numbers, and redundant discussion of thelike-numbered features typically is omitted for the sake of brevity.

DETAILED DESCRIPTION

[0031] In FIGS. 1-3, a first embodiment of a non-volatile memory array100 is presented. Memory array 100 includes a plurality of memory cellsM1 arranged in rows and columns. FIG. 1 provides a schematic diagram ofone memory cell M1, and a cross-sectional side view of the memory cellM1 and portions of two identical, adjacent memory cells in the same row.The cross-sectional side view is taken through a center of the memorycell M1 along the polysilicon wordline 7′ overlying the row of memorycells. Each memory cell M1 is a distinct, split gate transistor.

[0032] The rows and columns (FIGS. 2, 3) of memory cells M1 are formedin a deeply-diffused P-well 11 (FIGS. 4a, 5 a) in a P-type semiconductorsubstrate 1. Heavily-doped, N-type, shallow diffusion regions areprovided in P-well 11 in the form parallel pairs of lines 2′, 3′. Acolumn of the memory cells M1 overlaps each pair of implant region lines2′, 3′, which serve as local bitlines. A subportion of one of thediffusion region lines (denoted 2′) of the pair is the drain region 2 ofthe memory cell M1, and an adjacent subportion of the other diffusionregion line (denoted 3′) of the pair serves as the source region 3 ofthe memory cell M1. That is, each source diffusion region line 3′includes the source region 3 for all of the memory cells M1 of one ofthe columns of memory cells, and the associated, adjacent draindiffusion region line 2′ provides the drain region 2 for all of thememory cells of the column of memory cells. A subportion of P-well 11,denoted channel region 9, is between the source region 3 and the drainregion 2 of each memory cells. (The term “channel region” is used torefer to a subportion of the P-well 11 between the source and drainregions 3, 2 where a channel would form if the transistor turned on. Thechannel region is present even when the transistor is not on.)

[0033] Shallow trench isolation (STI) regions 4 (FIGS. 1, 5a) are formedin the P-well 11 in the form of lines that extend parallel to the drainand source diffusion region lines 2′, 3′. One of the STI region lines 4separates each of the adjacent pairs of the drain and source diffusionregion lines 2′, 3′, so that memory cells in the same row areelectrically isolated from each other. In an alternative embodiment, theSTI region lines are replaced by field oxide region lines.

[0034] A thin, tunnel oxide layer 5 is provided on the source side ofeach of the memory cells. The tunnel oxide layer is over, and in contactwith, the source region 3 and the a source-side subportion of the P-well11 surface over channel region 9. The tunnel oxide layer does notoverlie the drain region 2 of the memory cell, but rather is separatedfrom the drain region by a-region of a thicker dielectric layer 8, as isdiscussed below.

[0035] At each of the memory cells M1, an electrically isolatedrectangle of a first polysilicon layer overlies, and is in contact with,the tunnel oxide layer 5 over the source region 3 and the source-sidesubportion of the P-well 11 surface covered by tunnel oxide layer 5.This rectangle of polysilicon is the floating gate 6 of the memory cell.A second layer of polysilicon is formed into parallel wordlines 7′ thateach extend perpendicular to the diffusion region lines 2′, 3′. Each ofthe plural polysilicon wordlines 7′ overlies one of the rows of memorycells M1. The wordline 7′ extends integrally over the source region 3,floating gate 6, channel region 9, and drain region 2 of every memorycell of the row and over the isolation regions 4 that are betweenadjacent memory cells of the row.

[0036] At each memory cell M1, the subportion of the polysiliconwordline 7′ overlying the memory cell M1 functions as the control gate 7of the memory cell M1. An intervening, relatively-thick dielectric layer8 (e.g., oxide) separates the polysilicon wordline 7′ from theunderlying floating gate 6, from the drain-side portion of the P-well 11surface uncovered by the floating gate 6, and from drain region 2 of thememory cell M1. Dielectric layer 8 is much thicker than tunnel oxidelayer 5, and separates the floating gate 6 from the drain region 2. Thefloating gate 6, tunnel oxide layer 5, and the dielectric layer 8 arebetween the control gate 7 and the underlying source region 3.

[0037] The non-volatile memory cell M1 of FIG. 1 thus has anelectrically isolated floating gate 6 that is over and in contact with atunnel oxide layer 5 that itself is over and in contact with the sourceregion 3. The floating gate 6 is on the source-side of the memory cell,and terminates over the channel region 9. Hence, the floating gate 6does not extending over the drain-side of the channel region or over thedrain region 2. The control gate 7, on the other hand, extends over theentire channel region 9 and over the source and drain regions. Adielectric layer 8 separates the control gate from the P-well 11surface, and thus functions as a gate dielectric. Portions of dielectriclayer 8 also isolate and separate the control gate 7 from the floatinggate 6, and the floating gate 6 from the drain region 2. The arrangementof the floating gate 6 and control gate 7 is as a split gate transistor.

[0038] A schematic diagram of a portion of the memory array 100 is shownin FIG. 2. For simplicity, only three columns and two rows of memorycells M1 are shown. The basic operation of this small memory array isshown in Table I (FIG. 2a) as an illustration of the operation of alarger memory array comprised of any number of rows and columns ofmemory cells M1. A typical memory array will have a plurality of memorycells in each of a plurality of rows and columns.

[0039] Referring to FIG. 2 and Table 1, an erase operation erases all ofthe memory cells of a selected row. During the erase, the wordline 7′(denoted WL1) overlying the selected row, which includes the circledmemory cell M l, is biased to a negative high voltage, −Vpp, for aselected period of time, e.g., on the order of a few milliseconds. Thedeselected wordline 7′ (WL2) over of the deselected row of memory cellsis grounded. At the same time, for each of the columns, the drain regionlines 2′ (BL1 a, BL2 a, BL3 a) and the source region lines 3′ (BL1 b,BL2 b, BL3 b) are floating. Accordingly, the floating gates 6 of everymemory cell in the selected row (WL1) is biased, by capacitive coupling,to negative voltages such that electrons on the respective floating gate6 pass through the tunnel oxide layer 5 to the P-well 11 byFowler-Nordheim tunneling. As a result, the floating gates 6 of thememory cells of the selected row all become positively charged. Theerased state corresponds to the conductive state of the memory cell M1.The −Vpp voltage can be in the range −12V to −20V depending, forinstance, on the thickness of tunnel oxide layer 5, floating gatecoupling, and other memory cell construction details.

[0040] Practitioners will appreciate that one or more rows of the memorycells can be erased in a single erase operation, depending on how manywordlines 7′ are biased to the negative high voltage, −Vpp.

[0041] During a write operation for the selected (i.e., circled) memorycell M1 of FIG. 2, the wordline 7′ (i.e., the control gate 7) for theselected memory cell M1 (and the other memory cells of the same row) isbiased at positive high voltage, Vpp. Meanwhile, the drain region line2′ (BL2 a) for the selected memory cell M1 (and the other memory cellsof the same column) is grounded (0 V). In addition, the source regionlines 3′ (BL1 b, BL2 b, BL3 b) for the selected column and the othercolumns are allowed to float. The application of Vpp to the selectedwordline 7′ (i.e., to the control gate 7 of the selected cell) biasesthe floating gate 6 of the selected memory cell M1, by capacitivecoupling, to a positive voltage. As a result, at the selected memorycell M1, electrons pass from channel region 9 through the tunnel oxidelayer 5 to floating gate 6 by Fowler-Nordheim tunneling.

[0042] Note that, during the write operation, for the cells of theselected row, the source region line 3′ is floating and will take thesame potential as the drain region line 2′ because the selected memorycell is turned on during programming (the control gate voltage is veryhigh). The absence of a voltage bias between the drain and sourceregions of the selected memory cell during programming helps to avoidjunction breakdown and to avoid the emission of hot carriers. Hotcarriers are known to cause oxide and interface deterioration innon-volatile memories

[0043] Accordingly, during the write operation, the floating gate 6 ofthe selected memory cell M1 develops a net negative charge. This state,called the programmed state, corresponds to the non-conductive state(logical zero) of the selected memory cell M1. The positive Vpp voltagecan be in the range 12V to 20V, similarly as in the erase phase.

[0044] During the write operation, deselection of the memory cells onthe same row as the selected memory cell M1 is accomplished bycounterbiasing the drain region lines 2′ (BL1 a, BL3 a) of thedeselected columns of memory cells to a lower positive voltage, Vppx.(The source region lines 3′ (BL2 b, BL3 b) are allowed to float.) Thevalue of Vppx may be in the range of 3V to 7V, and generally depends onthe separation window between the erased and programmed state.Typically, Vppx is less than or equal to half of Vpp. The application ofVpp to the selected wordline 7′, together with the application of Vppxon the drain region lines 2′ of the deselected columns, will bias therespective tunnel oxide regions to a voltage equal or less than thedifference between Vpp and Vppx, which bias is too small to cause anysignificant Fowler-Nordheim programming. Accordingly, the floating gates6 of the deselected memory cells in the selected row will not beaffected.

[0045] During the write operation, there is a disturb path for thememory cells on the deselected rows 7′ (WL2), because the source regionlines 3′ of the deselected columns are biased to Vppx. Recall that thesource region lines 3′ float, and take the same potential as theircounterpart drain region line 2′. This disturb risk can be completelyavoided by biasing the deselected wordline 7′ (WL2) overlying thedeselected rows of memory cells to a voltage equal to or less than Vppx.The application of a voltage <Vppx on deselected wordline will bias therespective tunnel oxide regions to a voltage too small to cause anysignificant change in the floating gate charge.

[0046] During a read operation for the selected (i.e., circled) memorycell M1 of FIG. 2, all of the source region lines 3′ (BL1 b, BL2 b, BL3b) are connected to ground (0 V) and all of the drain region lines 2′(BL1 a, BL2 a, BL3 a) are biased to a low positive voltage, Vr, whichmay be ˜1V. Meanwhile, the selected wordline 7′ (WL1) overlying theselected memory cell M1 (and the other memory cells of the same row) isbiased to a low positive voltage, normally equal to the supply voltage,Vcc. The deselected wordlines 7′ (WL2) are grounded, in order to blockcurrent to the deselected rows of memory cells. A sense amplifier (notshown) detects whether the selected memory cell M1 turns on in responseto the application of Vcc to the wordline 7′ (i.e., the control gate 7)of the selected memory cell. If the selected memory cell M1 of FIG. 2 isin an erased state (i.e., logical one, with a net positive charge onfloating gate 6), then the application of Vcc to the selected wordline7′ will turn on the selected memory cell transistor. The conductivestate is interpreted as a logical one. On the other hand, if theselected memory cell M1 is in a programmed state (i.e., logical zero,with a net negative charge on floating gate 6), then the application ofVcc to wordline 7′, i.e., to the control gate 7, of the selected memorycell M1 will not turn on the transistor. The nonconductive state isinterpreted as a logical zero.

[0047] The read and write operations access independently any column ina memory block. Consequently, any number of columns (e.g., one or more)can be programmed and read simultaneously.

[0048]FIG. 3 shows an architecture of a non-volatile memory 100, inaccordance with one embodiment of the present invention. Parameters forthe erase, write, and read phases also are shown in FIG. 3.

[0049] Memory 100 is organized in blocks 22, with each block 22consisting of any number of rows and columns of memory cells M1. Thenumber of rows of memory cells M1 is normally a power of 2 (16, 32, 64,etc). Each row of memory cells M1 in the block 22 has a corresponding,overlying wordline 7′. All of the respective wordlines 7′ of a block 22are coupled to a row decoder 25 that selects the wordline bias duringthe erase, write and read operations. Each column of the block 22contains a selected number of memory cells that each overlap the samepair of drain and source region lines 2′, 3′. One end of each drainregion line 2′ is coupled through a pass transistor 15 to a main bitline16 (e.g., a metal bitline). All pass transistors 15 are controlled by afirst block select signal (BS1) that is produced by a block selectcircuit 24. The first block select signal (BS1) is provided to therespective gates of all of the transistors 15 via block select line 20.One end of each source region line 3′ is coupled through a passtransistor 18 to the ground line 19. All pass transistors 18 arecontrolled by a second block select signal (BS2) that is produced by ablock select circuit 23. The second block select signal (BS2) isprovided to the respective gates of all of the pass transistors 18 viablock select line 21. The, main bitlines 16 are biased through thebitline decoder circuit 26. During the read phase, a bitline decoder 26connects selected bitlines 16 to the sense amplifier 27, whichdetermines whether the particular memory cell coupled to the mainbitline is conductive (logical one), or nonconductive (logical zero).Normally, the, sense amplifier 27 processes eight bits at a time,although there is no limitation to the number of bits that can beprocessed (read).

[0050] Selection of a subset (e.g., one) of the blocks 22 from among theentire set of blocks 22 during erase, write, and read operations isperformed by a block decoder circuit 30 that is coupled to each of theblocks 22. The block decoder circuit 30 may be coupled to control theblock select circuit 24, row decoder 25, and block select 23 of eachblock 22.

[0051] During an erase operation, row decoder 25 selects the particularrow(s) of the selected block 22 that are to be erased, and provides ahigh negative voltage (−Vpp) to the overlying wordline 7′ (WL1).Meanwhile, block select circuitry 24 couples block select line 20 toground (BS1=0 V), which grounds the gates of pass transistors 15,ensuring that pass transistors 15 remain off. Block select circuitry 23couples the block select line 21 to ground (BS2=0 V), ensuring that passtransistors 18 remain off. Accordingly, the drain region lines 2′ andthe source region lines 3′ of the selected block 22 float. Bitlinedecoder 26 may either couple the main bitlines 16 to ground (0 V), orallow the main bitlines 16 to float.

[0052] The application of −Vpp to the selected wordline 7′ (WL1)overlying the selected row of memory cells M1 causes electrons on thefloating gate 6 of every memory cell of the row to pass through thetunnel oxide 5 to the underlying P-well 11, resulting in a net positivecharge on the floating gate 6. Accordingly, all memory cells in theselected row(s) are erased. Row decoder 25 may deselect other rows ofmemory cells by applying a ground voltage (0 V) to the wordline 7′ (WL2)overlying each of the deselected rows of memory cells of the block 22.

[0053] In a write operation, row decoder 25 applies a high positivevoltage (Vpp) to the selected wordline 7′ (WL1) overlying the selected(i.e., circled) memory cell M1. Row decoder 25 also applies the lowerpositive voltage Vppx (or smaller) to the deselected wordlines 7′ (WL2).Meanwhile, bitline decoder 26 causes the main bitline 16 for the columnthat includes the selected cell M1 to be grounded (0 V), and the mainbitlines 16 for the deselected columns to be set to Vppx. In addition,block select circuitry 24 provides a first block select signal (BS1)equal to Vpp to the gates of pass transistors 15 on block select line20. Accordingly, pass transistors 15 turn on, thereby causing the drainregion line 2′ (denoted BL2 a) for the selected memory cell M1 (and theother memory cells of the same column) to be at ground (0 V), and thedrain region lines 2′ (denoted BL1 a, BL3 a) for the deselected columnsto be at Vppx. In addition, block select circuit 23 couples block selectline 21 to ground (0 V), so that pass transistors 18 remain off.Accordingly, source region lines 3′ are floating, and will take the samepotential as the associated drain region line 2′.

[0054] The application of Vpp to the selected wordline 7′ (WL1)overlying the selected memory cell M1 causes electrons to pass from thechannel region 9 to the floating gate 6 through the tunnel oxide 5,leaving the floating gate 6 with a net negative charge. This state,called the programmed state, corresponds to the non-conductive state ofthe memory cell M1. The floating gates 6 of the deselected memory cellsin the same row (WL1) as the target cell do not accumulate such anegative charge, i.e., are unaffected, because of the application ofVppx to their respective drain region line 2′. The floating gates 6 ofthe memory cells in the deselected rows are unaffected, because of theapplication of Vppx to the deselected wordlines 7′ (WL2) by row decoder25.

[0055] During a read operation, row decoder 25 applies a positivevoltage (on the order of Vcc) to the selected wordline 7′ (WL1)overlying the selected (i.e., circled) memory cell M1. Row decoder 25also coupled the deselected wordlines 7′ (WL2) to ground, ensuring thatno current passes through the memory cells of the deselected rows.Meanwhile, bitline decoder 26 causes a selected number of the mainbitlines 16 to b& set to a low positive voltage Vr, e.g., 1 V, with Vrbeing less than Vcc. Block select circuit 24 provides a first blockselect signal (BS1) of Vcc on block select line 20 to the gates of passtransistors 15, which causes pass transistors 15 turn on, therebysetting the drain region lines 2′ (BL1 a, BL2 a, BL3 a) to Vr. Blockselect circuit 23 provides a second block select signal (BS2) of Vcc onblock select line 21 to the gates of pass transistors 18, which turns onpass transistors 18. Accordingly, pass transistors 18 couple sourceregion lines 3′ (BL1 b, BL2 b, BL3 b) to ground line 19. As a result,the selected memory cell M1, which has its drain region line 2′ biasedto Vr, its source region line 3′ grounded, and its overlying wordline 7′(WL1) at Vcc, will conduct if its floating gate 6 is storing a positivecharge (i.e., erased state), and will not conduct if its floating gate 6is storing a negative charge (i.e., programmed state). Bitline decoder26 couples the main bitline 16 of the column including the selectedmemory cell M1 to the sense amplifier 27, which determines whether theselected memory cell M1 is conductive or not conductive. Deselectedmemory cells in other rows do not turn on, because the deselectedwordlines 7′ (WL2) are set to ground by row decoder 25.

[0056] In view of the above discussion of FIGS. 1-3, practitioners willappreciate various features of non-volatile memory 100 and non-volatilememory cell M1. For example, non-volatile memory cell M1 includes aselect transistor-comprising a source region 3, drain region.2, channelregion 9, and control gate 7. This select transistor controls access tothe floating gate 6 of the memory cell, similar to an EEPROM. Yet, thememory cell does not have the two separate transistors of an EEPROM.Accordingly, the memory cell M1 can be much smaller than an EEPROM cell.For instance, the size of a memory cell is sometimes reported in termsof the feature size squared, or F². A memory cell in accordance with thepresent invention may have an area of 8-10 F², which is comparable to aFLOTOX-style flash memory cell. By comparison, a standard EEPROM mayhave an area of 40-50 F².

[0057] Reduced size is also made possible by elimination of certaincontacts at each of the memory cells. In particular, unlike conventionalEEPROMs or flash memory cells, there is no need to have a separatecontact to the bitline and wordline at each memory cell. Rather, fornon-volatile memory 100, one contact is provided at the end of the drainregion line 2, and one contact is provided to the source region line 3,for an entire column of memory cells. Further, the need for contactbetween particular memory cells and the wordline 7′ is accomplished byusing an subportion of the overlying wordline 7′ as the control gate 7of all of the respective memory cells of the row.

[0058] Cell size reduction in comparison to an EEPROM is also achievedby the fact that only low voltages (0 V or Vppx) are placed on the bitlines 16 (and hence on the drain region lines 2′ and source region lines3′). Vppx is, in some embodiments, 3 to 7 Volts, which is less than halfof Vpp.

[0059] Further, reliablce operation is obtained relative to conventionalflash memories in that, during a write operation, there no bias betweenthe drain and the source regions of the memory cell. This avoidsjunction breakdown and the generation of hot carriers.

[0060] Further, the risk of disturbing some memory cells while accessinganother memory cell, as is common with flash memories, is eliminated, orat least largely eliminated. Such reliability is obtained, for instance,by: (1) the provision of dielectric isolation regions 4-between-adjacentpairs of source and drain region lines 3′, 2′; (2) the provision of aselect transistor to control access to the floating gate 6; and (3) theability to bias deselected wordlines 7′ to Vppx. The use of low voltageon the columns (e.g., 0 V or Vppx on the drain and source region lines2′, 3′) practically eliminates the bitline disturb.

[0061] Two exemplary processes for making the memory cells M1 of thenon-volatile memory of FIGS. 1-5 are described below. A first processimplementation is based on LOCOS field oxidation. Referring to FIGS.4a-4 e ; the field oxide 36 substitutes for the STI regions 4 of FIG. 1.Such a process may be used, for instance, where feature sizes are 0.35micron and above. The second implementation, which is shown in FIGS.5a-5 d, uses shallow trench isolation (STI), as depicted in FIG. 1. Thissecond embodiment lends itself to processes having feature sizes smallerthan 0.35 microns. Other methods for making the memory cells describedabove may present themselves to practitioners in view of the disclosureherein and known methods in the art.

[0062] In the first implementation, the processing starts with a P-typesilicon wafer 1 (FIG. 4a), into which a P-well 11 is implanted anddiffused. The memory cells are formed in P-well 11. A pad oxide/thinnitride layer 36 is deposited on top of P-well 11. The active mask isthen realized by etching openings 33 in the pad oxide/nitride layer 36.An N+ implant is performed through photoresist mask 34. A small areaself-aligned to the edge of the field mask is implanted, followed by adiffusion step. Accordingly, the parallel pairs of drain and sourceregion lines 2′, 3′ (FIGS. 2, 3) are formed in P-well 11. A LOCOS fieldoxidation step follows the formation of the drain and source diffusionregion lines 2′, 3′. The LOCOS field oxidation step produces parallellines of field oxide 36 in the P-well 11. Each line of field oxide 36 isbetween adjacent pairs of the drain and source region lines 2′, 3′, andis parallel to the drain and source region lines 2′, 3′. At particularmemory cells, the drain and source regions 2, 3 are realized in facingbird's beak areas of adjacent of field oxide lines 36, as shown in FIG.4b. Channel region 9 is between the drain and source regions 2, 3. Eachof the field oxide lines 36 isolates the source regions 3 of the memorycells of one column from the drain regions 2 of an adjacent column ofthe memory cells.

[0063] Next, a thin layer of tunnel oxide 5 is grown over channel region9. The tunnel oxide thickness is on the order of 7-11 nm, which is thepractical range for non-volatile memories. The tunnel oxide area canextend over the whole wafer (outside field oxide) or it may berestricted to the memory area only. The choice is dependent on theparticular process implementation in adding the low voltage module.

[0064] A first polysilicon layer 39 is then deposited over the topsurface of the wafer so as to cover (and contact) the tunnel oxide 5. Adielectric layer 40 of oxide, nitride, and oxide layers is formed on topof the first polysilicon layer 39 (FIG. 4c). Then, using standardphotolithography, the oxide/nitride/oxide (ONO) layer 40,and the firstpolysilicon layer 39 are etched into stripes that are parallel to thedrain and source region lines 2′, 3′. Each of the stripes of firstpolysilicon layer 39 overlie a subportion-only of a top surface of thefield oxide 36, a source-side bird's beak region of the field oxide 36,the source region 3,′ and a source-side subportion-only of the P-well 11top surface over channel region 9. A side of the polysilicon layer 39terminates over channel region 9. Accordingly, drain region 2 and adrain-side subportion-only of the P-well 11 top surface over channelregion 9 are not covered by the patterned first polysilicon layer 39.

[0065] Using ONO layer 40 as a mask, a fresh layer of oxide 41 is grownas the gate oxide for the select transistor portion of memory cell M1.The oxide layer 41 is disposed on the P-well 11 surface over the portionof channel region 9,uncovered by patterned first polysilicon layer 39.Oxide layer 41 separates the first polysilicon layer 39 from the drainregion 2. Oxide layer 41 has an appropriate thickness, e.g., in therange of 250-400 Å, to sustain a gate voltage of ±12 to ±20V.

[0066] Then, a second polysilicon layer 42 is deposited (FIG. 4d) overONO layer 40 and oxide layer 41. The second polysilicon layer 42 is thenetched through a photoresist mask into parallel stripes, i.e., wordlines7′, that each extend perpendicularly to the drain and source regionlines 2′, 3′ (FIGS. 2, 3) and to the stripes of first polysilicon layer39. Each wordline 7′ integrally overlies every memory cell of a row ofmemory cells, as well as the field oxide line 36 between adjacent memorycells. Then, in the same etch chamber and without removing thephotoresist mask, the stripes of first polysilicon layer 39 are thenetched through using the polysilicon layer 42 stripes as a mask. Thisforms isolated rectangles of the first polysilicon layer 39 at eachmemory cell, thereby forming floating gates 6 (FIG. 4e) under thewordlines 7′. As mentioned above, a subportion of the wordline 7′ overeach memory cell M1 of the row serves as the control gate 7 of thememory cell transistor. ONO layer 40 separates the control gate 7 fromthe floating gate 6, and oxide layer 41 separates the control gate 7from channel region 9 and drain region 2. Other process steps to obtainstandard CMOS devices and to provide contacts and interconnections forthese devices are well known in the industry and will not be detailedhere.

[0067] In the second implementation, the processing starts with a P-typesilicon substrate 1 (FIG. 5a), into which a P-well 11 is implanted anddiffused. A dielectric layer 46 is then deposited as a mask for the STIprocess. The active mask is realized by etching parallel STI trenches 45in the top surface of P-well layer 11. Each STI trench 45 has twovertical sidewalls that extending from one end of the trench to theother. The columns of memory cells are formed between a pair of the STItrenches 45. In particular, an N+ dopant is implanted in the facingsidewalls of two adjacent STI trenches 45. The N+ doping is done byangle implants, and in a manner that provides a line of the N+ dopant inthe two sidewalls that extends from one end of the trench to the other.The source of the dopant ions is at an acute or oblique angle to thesubstrate during the implanting. The implants may be annealed duringsubsequent process steps. As a result, the drain region 2 of eachnascent memory cell M1 a column of the memory cells is at and inward ofa vertical sidewall 45 of one of the STI trenches 45, and the sourceregion 3 of the same nascent memory cell M1 is at and inward of a facingvertical sidewall of the next STI trench 45, with the channel region 9of P-well 11 between them.

[0068] After the implanting step, the STI trenches 45 are filled with adielectric 47, which may be an oxide. The STI dielectric 47 may beformed by depositing a blanket plasma oxide layer, and then polishingthe plasma oxide layer to remove portions over and outward of the STItrench 45. The STI dielectric 47 isolates the source regions 3 of memorycells of one column of the memory from the drain regions 2 of the memorycells of an adjacent column.

[0069] Subsequently, at each memory cell, a tunnel oxide layer 5 isgrown over the source region 3 and a source-side subportion-only of thechannel region 9, as mentioned above. A first polysilicon layer 39 isthen deposited over the top surface of the wafer so as to cover (andcontact) the tunnel oxide layer 5 at each memory cell. An ONO layer 40is formed on top of the first polysilicon layer 39 (FIG. 4c). Then,using standard photolithography, the ONO layer 40 and the firstpolysilicon layer 39 are etched into stripes that are parallel to thedrain and source region lines 2′, 3′ (FIGS. 2, 3, 5 d). The stripes offirst polysilicon layer 39 overlie a top, source-side subportion-only ofthe STI dielectric 47, the source region 3, and a source-sidesubportion-only of the P-well 11 surface over channel region 9. Asidewall of first polysilicon layer 39 terminates over channel region 9,so that the drain region 2 and a drain-side subportion-only of theP-well 11 top surface over the channel region 9 of the respective memorycell are not covered by the stripe of the first polysilicon layer 39.

[0070] Using the ONO layer 40 as a mask, a fresh layer of oxide 41 is onthe P-well 11 top surface over channel region 9 and drain region 2,thereby forming a gate oxide for the select transistor portion, of thememory cell. The oxide layer 41 separates, first polysilicon layer 39from drain region 2 and channel region 9. Oxide layer 41 has athickness, e.g., in the range of 250-400 Å, sufficient to sustain a gatevoltage of up to ±20V.

[0071] Then, a second polysilicon layer 42 is deposited (FIG. 5c) overthe wafer top surface. The second polysilicon layer 42 is etched througha photoresist mask into parallel wordline 7′ stripes that each extendperpendicularly to the drain and source region lines 2′, 3′ (FIGS. 2, 3)and the stripes of first polysilicon layer 39. Each wordline 7′integrally overlies every memory cell of a row of the memory cells, aswell as the STI dielectric 47 that is between adjacent memory cells ofthe row. Then, in the same etch chamber and without removing thephotoresist mask, the stripes of first polysilicon layer 39 are etchedthrough using the second polysilicon layer 42 stripes as a mask. Thisstep forms isolated rectangles of the first polysilicon layer 39,thereby forming a floating gate 6 (FIG. 5d) under the wordlines 7′ ateach memory cell. As mentioned above, the subportion of the wordlinestripe 7′ over the particular memory cell M1 serves as the control gate7 of the memory cell transistor. ONO layer 40 separates the control gate7 from the floating gate 6, and oxide layer 41 separates the controlgate 7 from channel region 9 and drain region 2. Other process steps toobtain standard CMOS devices and to provide contacts andinterconnections for these devices are well known in the industry andwill not be detailed here.

[0072] A second-embodiment of a non-volatile memory, denoted asnon-volatile memory 101, and exemplary methods of making it, aredisclosed in FIGS. 6-8. A main building block of the non-volatile memory101 is a memory cell M2.

[0073] Nonvolatile memory 101 and memory cells M2 of FIGS. 6 and 7 arebasically identical to memory 100 and memory cell M1 of FIGS. 1-3,except that the P-well 11, in which the memory cells M2 are formed, isitself formed in an N-well 10. N-well 10 is deeply diffused into P-typesemiconductor substrate 1. Both P-well 11 and N-well 10 are coupled tovoltage sources. Further discussion of the structural aspects of FIGS. 6and 7 is not necessary, since those figures otherwise include the samestructures and the same reference numbers as FIGS. 1 and 2. The readershould consult the discussion above, which is incorporated herein byreference.

[0074] The basic operation of the portion of memory 101 shown in FIG. 7is provided in Table 2 (FIG. 7a) as an illustration of the operation ofthe larger memory array 101 comprised of any number (e.g., a plurality)of columns and rows of memory cells M2. The parameter values for memoryarray 101, as set forth in Table 2 (FIG. 7a), differ from those formemory array 100 (Table 1, FIG. 2) due to the disposition of P-well 11in N-well 10.

[0075] Referring to FIG. 7 and Table 2, an erase operation erases all ofthe memory cells of a particular row or rows. During the erase, thewordline 7′ (denoted WL1) overlying the selected row, which includes thecircled memory cell M2, is biased to ground (0 V), while the underlyingP-well 11 and N-well 10 are biased to a positive high voltage, Vpp, fora time on the order of a few milliseconds. The deselected wordlines 7′(denoted WL2) overlying the deselected rows of memory cells also arebiased to Vpp, the same bias that is applied to wells 10, 11. At thesame time, all of the drain region lines 2′ and source region lines 3′are kept floating. The floating gates 6 of the memory cells of theselected row are biased, by capacitive coupling, to voltages muchsmaller than the voltage of the underlying P-well 11, such thatelectrons pass from the respective floating gates 6 through theunderlying tunnel oxide layer 5 into the P-well 11 by Fowler-Nordheimtunneling. Accordingly, the floating gates 6 of all of the memory cellsof the selected row (WL1) become positively charged. The erased statecorresponds to the conductive state of the memory cell. The Vpp voltagecan be in the range 12V to 20V depending on tunnel oxide thickness,floating gate coupling and other cell construction details.

[0076] Practitioners will appreciate that one or more rows of the memorycells of memory array 101 can be erased, depending on how many wordlines7′ are, coupled to ground.

[0077] During a write operation for the selected (i.e., circled) memorycell M2 of FIG. 7, the overlying wordline 7′ (WL1), which includes thecontrol gate 7 for each of the cells of the row, is biased at a positivehigh-voltage, Vpp. Meanwhile, the drain region line 2′ of the selectedmemory cell M2 (and for the other memory cells of the same column) isset to ground (0 V). The wells 10 and 11 also are set to ground (0 V).The source region lines 3′ (BL1 b, BL2 b, BL3 b) are allowed to float.By capacitive coupling, the floating gate 6 of the selected memory cellM2 is biased to a positive Voltage such that electrons pass from thechannel region 9 through the tunnel oxide layer 5 to the floating gate 6by Fowler-Nordheim tunneling. Alternatively, N-well 10 may be coupled toa positive voltage (>0 V) to prevent possible latch up.

[0078] Note that, during the write operation, the source region line 3′is floating and will take the same potential as the drain region line 2′because the selected memory cell transistor is turned on duringprogramming (the gate voltage is very high). The absence of a voltagebias between the drain and source regions during programming helps toavoid junction breakdown and to avoid the emission of hot carriers. Hotcarriers especially are well known to cause oxide and interfacedeterioration in non-volatile memories

[0079] Accordingly, during the write operation, the floating gate 6 ofthe selected memory cell M2 develops a net negative charge. This state,called the programmed state, corresponds to the non-conductive state(logical zero) of the selected memory cell M2. The positive Vpp voltagecan be in the range 12V to 20V, similarly as in the erase phase.

[0080] During the write operation, deselection of the memory cells inthe same row as the selected memory cell M2 is accomplished bycounterbiasing the drain region lines 2′ (BL1 a, BL3 a of FIG. 7) of thedeselected columns of memory cells to a lower positive voltage, Vppx.The value of Vppx may be in the range of 3V to 7V, and generally dependson the desired window between the erased and programmed state.Typically, Vppx is less than or equal to half of Vpp. The source regionlines 3′ (BL2 b, BL3 b) for the deselected columns of memory cells arefloating. The application of Vpp to the selected wordline 7′, togetherwith the application of Vppx on the drain region lines 2′ of thedeselected columns, will bias the respective tunnel oxide regions to avoltage equal or less than the difference between Vpp and Vppx, whichbias is too small to cause any significant Fowler-Nordheim programming.Accordingly, the floating gates 6 of the deselected memory cells in theselected row will not be affected.

[0081] During the write operation, there is a disturb path for the cellson the deselected rows (WL2) of memory, because of the source regionlines 3′ that are biased to Vppx. Recall that the source region lines 3′float, and take the same potential (Vppx) as their counterpart drainregion line 2′. This disturb risk can be completely avoided by biasingthe wordlines 7′ (WL2) overlying the deselected rows of memory cells toa voltage equal to or less than Vppx. The application of a voltage <Vppxon deselected wordline will bias the respective tunnel oxide regions 5to a voltage too small to cause any significant change in the floatinggate charge.

[0082] During the read phase, all of source region lines 3′ (BL1 b, BL2b, BL3 b) and the wells 10, 11 of FIG. 7 are connected to ground (0 V).Meanwhile, all of the drain region lines 2′ (BL1 a, BL2 a, BL3 a) arebiased to a low positive voltage Vr, which may be ˜1V. The selectedwordline 7′ for the selected memory cell M2 is biased to a low voltage,in the range of the supply voltage Vcc. The deselected wordlines 7′(WL2) are coupled to ground (0 V) in order to block the current to thememory cells of the deselected rows. According, if memory cell M2 is inan erased state (i.e., logical one, with a net positive charge onfloating gate 6, then the application of Vcc to the selected wordline7′. A sense amplifier (not shown) detects whether the selected memorycell M2 turns on in response to the application of Vcc to the wordline7′ (i.e., the control gate 7) of the selected memory cell. On the otherhand, if memory cell M2 is in a programmed state (i.e., logical zero),with a net negative charge on floating gate 6, then the application ofVcc to the selected wordline 7′, i.e., to the control gate 7, of theselected memory cell M2 will not turn on the transistor, i.e., thetransistor is not conductive.

[0083]FIG. 8 shows an architecture of a non-volatile memory 101, inaccordance with one embodiment of the present invention. Parameters forthe erase, write, and read phases also are shown in FIG. 8. Thearchitecture of memory 101 of FIG. 8 is very similar to the architectureof memory 100 of FIG. 3, and bears similar reference numbers. Hence, thereader is referred to the discussion of FIG. 3, which is incorporatedherein by reference. Accordingly, the following discussion of memory 101that, follows can be abbreviated by focusing on the differences betweenmemory 101 and memory 100.

[0084] Referring to FIG. 8, memory 101 is organized in blocks 22. Eachblock 22 consists of a selected number of rows and columns of memorycells M2. The number of rows of memory cells (i.e., the number ofwordlines 7′) is normally a power of 2 (16, 32, 64, etc). All of theblocks 22 are formed in a single P-well 11, which itself is formed in asingle N-well 10 of P-substrate 1 (FIG. 6). A well bias circuit 29 iscoupled to the P-well 10 and N-well 11 by connections 28, 27,respectively. Well bias circuit 29 provides a plurality of bias voltagesto P-well 10 and N-well 11. The bias differs for the various operationsof the memory. Alternatively, a plurality of separate P-wells 11 may beprovided in one N-well 10, with each P-well 11 including one ormore-blocks 22, or each block 22 may be provided in a separate P-well 11and N-well 10.

[0085] With the exception of building P-well 11 in N-well 10, andproviding a controllable well bias circuit 29 to bias wells 10 and 11,the structure of memory 101 of FIG. 8 is the same as that of memory 101of FIG. 3. Hence, the above discussion of FIG. 3 is incorporated hereinby reference.

[0086] The operation of memory 101 of FIG. 8 is very similar to theoperation of memory 100 of FIG. 3 (compare FIGS. 2, 2a, and 3 to 7, 7 a,and 8, respectively). The difference in operation of memory 101 versusmemory 100 stems from the fact that memory 101 is built in a P-well 11and N-well 10 of P-substrate 1, and has bias circuitry for P-well 11 andN-well 10.

[0087] During an erase operation, well bias circuitry 29 of FIG. 8provides a positive voltage Vpp to both N-well 10 and P-well, 11 viaconnections 28 and 27, respectively. Biasing N-well 10 and P-well 11 toVpp during the erase operation, while the selected wordline 7′ isgrounded, causes electrons to pass from the floating gate 6 of theselected memory cell M2 to the P-well 11. The floating gates 6 of thedeselected rows are not affected, because the deselected wordlines alsoare biased to Vpp.

[0088] During read and write operations, well bias circuitry 29 of FIG.8 biases N-well 10 and P-well 11 to ground (0 V) via connections 28 and27, respectively. Alternately, N-well 10 can be biased to a slightlypositive voltage, to prevent accidental junction turn-on.

[0089] Other than the biasing of the wells 10 and 11, and the differentvoltages applied to the wordlines 7′ during the write operation, memory101 operates with the same parameters in the erase, write, and readoperations as memory 100 of FIG. 3, which is discussed above. Hence,further discussion is not required.

[0090] Exemplary processes for making the memory cells M2 of thenon-volatile memory l 01 of FIGS. 6, 7, and 8 are provided in FIGS. 9a-9e and 10 a-10 e. The processes of FIGS. 9a-9 e, and 10 a-10 d areessentially identical to the processes of FIGS. 4a-4 e and 5 a-5 d,respectively. The difference between the embodiments is related to thesemiconductor substrate 1. In particular, in the embodiments of FIGS.9a-9 e and 10 a-10 d, the processing starts with a P-type silicon wafer1 (FIG. 9a), into which an N-type dopant is implanted and deeplydiffused, forming the N-well 10. Next, a P-type dopant is implanted anddeeply diffused in the N-well 10, forming P-well 11 Since the processesof FIGS. 9a-9 e and 10 a-10 d are otherwise identical to the processesof FIG. 4a-4 e and 5 a-5 d, respectively, it is not necessary todescribe the processes of FIGS. 9a-9 e and 10 a-10 d any further. Thereader should refer to the prior discussion of FIGS. 4a-4 e and 5 a-5 d,which is incorporated here by reference.

[0091] The invention is not limited to the exemplary embodimentsdescribed above. Other embodiments may be suggested to practitioners bythe disclosure herein. For instance, while some structures areidentified herein as having a P-type conductivity, and other materialsare identified as having an N-type conductivity, the conductivity typescan be switched. Such a switch could change the polarity of the voltagesthat would need to be applied in the read, write, and/or erase phases,but in a predictable manner.

1. A semiconductor device including a plurality of non-volatile memorycells arrayed in rows and columns, the semiconductor device comprising:(a) a semiconductor substrate comprising a first region of a firstconductivity type; (b) a plurality of parallel pairs of parallel implantregion lines of a second conductivity type in the first region, whereineach of the columns of the non-volatile memory cells overlaps arespective one of the pairs of the implant regions lines, respectivesubportions of one of the implant region lines of the pair compriserespective source regions for the respective memory cells of therespective column, respective subportions of the other implant regionline of the pair comprise respective drain regions for the respectivememory cells of the column, and respective subportions of the firstregion between the respective source and drain regions of the respectivememory cells comprises respective channel regions of the respectivememory cells of the column; (c) one or more dielectric region lines inthe first region and parallel to the implant region lines, wherein atleast one of the dielectric region lines is between adjacent said pairsof the implant region lines; (d) a tunnel dielectric layer formed in avicinity of the source region of each of the non-volatile memory cells,wherein the tunnel dielectric layer is in contact with the respectivesource region; (e) a plurality of regions of a first polysilicon layer,wherein each said non-volatile memory cell has one of the firstpolysilicon layer regions over the source region and over and in contactwith the tunnel dielectric layer, the first polysilicon region being afloating gate that terminates over the channel region without extendingto the drain region of the memory cell; (f) a plurality of lines of asecond polysilicon layer each extending perpendicularly to the implantregion lines, wherein each said second polysilicon layer line integrallyoverlies all of the memory cells of a row and the dielectric region linebetween adjacent memory cells of the row, and a respective subportion ofthe second polysilicon layer line is a control gate of each said memorycell of the row; and (g) at each of the non-volatile memory cells, adielectric layer separating the second polysilicon layer line from theregion of, first region surface over the channel region, and the drainregion.
 2. The semiconductor device of claim 1, wherein the first regionis formed in a second region of the semiconductor substrate, the secondregion is of the second conductivity type, and the semiconductorsubstrate is of the first conductivity type.
 3. The semiconductor deviceof claim 1, wherein the regions of the first polysilicon layer each havea rectangular shape.
 4. The semiconductor device of claim 1, wherein thedielectric region lines comprise a field oxide.
 5. The semiconductordevice of claim 1, wherein the dielectric region lines each comprise anoxide layer formed in a trench in the first region.
 6. The semiconductordevice of claim 1, wherein the semiconductor substrate is of the firstconductivity type, and the first region is deeply diffused in thesemiconductor substrate.
 7. The semiconductor device of claim 1, furthercomprising a plurality of main bitlines coupled to a bitline decoder,and a plurality of pass transistors, wherein each said implant regionline that includes the drain regions is coupled at an end thereof to arespective one of said main bitlines through one of the passtransistors.
 8. The semiconductor device of claim 1, further comprisinga plurality of pass transistors, wherein each said implant-region linethat comprises the source regions is coupled at an end thereof to areference voltage source through a respective one of the passtransistors.
 9. The semiconductor device of claim 8, further comprisingat least one sense amplifier coupled to the bitline decoder.
 10. Thesemiconductor device of claim 1, further comprising a plurality of firstand second pass transistors, wherein one of the first pass transistorsis coupled to a respective one of the implant region lines of each pairof implant region lines, one of the second pass transistors is coupledto the other one of the implant region lines of the pair of implantregion lines, the first pass transistors have a common control line foroperating the first pass transistors, and the second pass transistorshave a common control line for operating the second pass transistors.10. A semiconductor device comprising: a first region of a firstconductivity type in a semiconductor substrate; at least one pair ofparallel implant region lines of a second conductivity type in saidfirst region; and for each pair of parallel implant region lines, acolumn of plural non-volatile memory cells overlapping the respectivepair of implant region lines, wherein one of the implant region lines ofthe pair includes a respective source region for each of the memorycells of the column, and the other implant region line of the pairincludes a respective drain region for each of the memory cells of thecolumn, with a respective subportion of the first region between thesource and drain region of each of the memory cells comprising a channelregion for the respective memory cell.
 11. The semiconductor device ofclaim 10, wherein each of the non-volatile memory cells comprises: atunnel dielectric layer in contact with one of the implant region linesof the pair of implant region lines; an electrically isolated floatinggate over and in contact with the tunnel dielectric layer and extendingonly part of a distance between the source and drain regions; and acontrol gate over the floating gate and extending the entire distancebetween the source and drain regions; and a dielectric layer between thecontrol gate and a surface of the first region.
 12. The semiconductordevice of claim 11, wherein the tunnel dielectric layer is in contactwith the implant region line that includes the source regions for thememory cells of the column.
 13. The semiconductor device of claim 1 1,wherein there are a plurality of said pairs of parallel implant regionlines in the first region, a plurality of the columns of thenon-volatile memory cells, and a plurality of rows of the non-volatilememory cells across said columns, and further comprising: a plurality ofparallel dielectric isolation region lines parallel to the implantregion lines, wherein one of the dielectric isolation region lines isbetween adjacent said columns of the memory cells; and a plurality ofparallel conductive wordlines extending perpendicularly across theimplant region lines, wherein each said wordline integrally overlies thememory cells of one of the rows of the memory cells and the dielectricisolation region line between adjacent memory cells of the row, and arespective subportion of the wordline is the control gate for each ofthe respective memory cells of the row.
 14. The semiconductor device ofclaim 13, further comprising a row decoder circuit coupled to each ofthe plurality of wordlines.
 15. The semiconductor device of claim 13,further comprising a plurality of main bitlines, a plurality of firstpass transistors, and a plurality of second pass transistors, and a mainbitline decoder circuit coupled to the main bitlines, wherein for eachcolumn of non-volatile memory cells, the implant region line includingthe drain regions is coupled to a respective one of the main bitlines ofthough one of the first pass transistors, and the implant region lineincluding the source regions is coupled to a reference voltage sourcethrough one of the second pass transistors.
 16. The semiconductor deviceof claim 10, wherein each of the non-volatile memory cells of the columncomprises an electrically isolated floating gate and a control gate overthe floating gate.
 17. The semiconductor device of claim 16, whereinthere are a plurality of the pairs of implant region lines and aplurality of the columns of non-volatile memory cells; and furthercomprising a plurality of wordlines each extending transversely to thepairs of implant region lines, with each said wordline integrallyoverlying an entire row of the non-volatile memory-cells, wherein arespective subportion of the wordline is the control gate for each ofthe respective memory cells of the row.
 18. The semiconductor device ofclaim 17, further comprising a plurality of main bit lines, wherein eachof said implant region line comprising the drain regions of each saidcolumn includes is coupled to the one of the main bitlines through apass transistor.
 19. The semiconductor device of claim 18, wherein theimplant region line comprising the drain regions of each respective saidcolumn includes only a single contact, and the associated implant regionline comprising the source regions of the column includes only a singlecontact.
 20. The semiconductor device of claim 17, wherein the implantregion line comprising the drain regions of each respective said columnincludes only a single coupling to a main bit line, and the associatedimplant region line comprising the source regions of the column includesonly a single coupling to a reference voltage source.
 21. Asemiconductor device comprising: at least one block of non-volatilememory cells arrayed in rows and columns in a first region of a firstconductivity type in a semiconductor substrate; a plurality parallelpairs of parallel implant region lines of a second conductivity type inthe first region, wherein each said column of the memory cells overlapsone pair of the implant region lines, wherein one of the implant regionlines comprises the source region for each of the memory cells of thecolumn, and the other of the implant region lines comprises the drainregion for each of the memory cells of the column; a plurality offloating gates, wherein each of the memory cells includes a floatinggate over the source region of the memory cell; a tunnel dielectriclayer between the floating gate of each memory cell and the underlyingsource region; at least one dielectric isolation region, wherein one ofthe dielectric isolation regions is between adjacent columns of thememory cells; a plurality of conductive wordlines traversing the implantregion lines, wherein each said wordline integrally overlies the memorycells of one of the rows and the dielectric isolation region betweenadjacent memory cells of the row, wherein a respective subportion of thewordline is a control gate for each respective memory cell of the row;dielectric material separating the wordline from a surface of the firstregion and from the floating gate at each of the memory cells.
 22. Amethod of making a nonvolatile memory including a plurality ofnon-volatile memory cells in rows and columns, the method comprising:providing a first region of a first conductivity type in a semiconductorsubstrate; forming a plurality of parallel pairs of implant regions inthe first region in the form of parallel lines; forming dielectricisolation region lines in the first region, said isolation region linesbeing parallel to the implant region lines, wherein one of the isolationregion lines is between adjacent pairs of the implant region lines,wherein respective subportions of one of the implant region lines ofeach pair will be a source region for each of a plurality of memorycells in a column of the memory cells, an adjacent respective subportionof the other of the implant region lines of the pair will be a drainregion for each of the memory cells of the column, and a respectiveintervening portion of the first region between the diffusion regionlines of the pair will be a channel region of the respective memorycell; forming a plurality of tunnel dielectric layers on a top surfaceof the first region, with each of the memory cells including one of thetunnel dielectric layers in contact with the source of the memory cell;depositing and patterning a first polysilicon layer toobtain-polysilicon stripes, wherein the tunnel oxide layer at each ofthe memory cells is in contact with one of the first polysilicon layerstripes; forming a first dielectric layer over a top surface of each ofthe first polysilicon layer stripes; depositing a second polysiliconlayer over the first dielectric layer, and patterning the secondpolysilicon layer to obtain stripes perpendicular to the pairs ofimplant region lines, with each said second polysilicon layer stripeoverlying a plurality of memory cells of a row of the memory cells, thesecond polysilicon layer stripe being entirely separated from a surfaceof the first region by a dielectric layer; and etching the firstpolysilicon layer using the second polysilicon layer stripes as a mask,in order to produce a rectangle of the first polysilicon layer at eachof the memory cells.
 23. The method of claim 22, wherein the firstregion is diffused in a second region of the second conductivity typethat is more deeply diffused into the semiconductor substrate, and thesemiconductor substrate is of the first conductivity type.
 24. Themethod of claim 22, wherein first region is diffused into thesemiconductor substrate, the semiconductor substrate also being of thefirst conductivity type.
 25. The method of claim 22, wherein the firstand second polysilicon layers are etched in a single etch step.
 26. Themethod of claim 22, further comprising forming a plurality of dielectricisolation region lines in the first region, wherein one said dielectricisolation region is between adjacent columns of the memory cells andextends parallel to the implant region lines.
 27. The method of claim26, wherein forming a plurality of dielectric isolation region linescomprises forming a plurality of parallel trenches in the surface of thefirst region, and filling the trenches with a dielectric material. 28.The method of claim 27, wherein forming a plurality of implant regionlines in the in the first region comprises implanting ions of the secondconductivity type into the first region through sidewalls of thetrenches prior to filling the trenches with the dielectric material. 29.The method of claim 22, wherein forming a plurality of dielectricisolation region lines comprises forming a plurality of parallel fieldoxide lines, with each of the field oxide lines being formed betweenadjacent pairs of the implant region lines.
 30. A method for operating anon-volatile memory, the method comprising: providing a non-volatilememory comprising rows and columns of non-volatile memory cells formedin a first region of a first conductivity type in a semiconductorsubstrate, wherein each of the memory cells has a floating gate overlaidby a control gate, each column of the memory cells overlaps one pair ofa plurality of parallel pairs of parallel implant region lines of asecond conductivity type formed in the first region, with one of theimplant region lines forming respective drain regions for the memorycells of the column, the other implant region line of the respectivepair forming respective source regions for the memory cells of thecolumn, and a plurality of wordlines each integrally overlying one ofthe rows of memory cells, with the control gates of each of the memorycells of the respective row being a respective subportion of theoverlying wordline; reading from a selected memory cell by applyingappropriate low positive voltages on the wordline overlying the selectedmemory cell and on the implant region line forming the drain for theselected memory cell, while the implant region line that includes thesource region for the selected memory cell is grounded; and writing to aselected memory cell by applying an appropriate high positive voltage onthe wordline overlying the selected memory cell and grounding theimplant region line that includes the drain region for the selectedmemory cell, while the implant region line forming the drain regions foreach deselected said column of the memory cells and the wordline foreach deselected said row of the memory cells are biased at low voltagelevels.
 31. The method of claim 30, wherein the first conductivity typeis P-type, the first region is deeply diffused in the semiconductorsubstrate, and the semiconductor substrate is P-type, and furthercomprising: and further comprising: erasing a selected row of the memorycells by applying a negative high voltage level on the overlyingwordline, while grounding the wordline overlying each deselected saidrow of memory cells.
 32. The method of claim 30, wherein the firstconductivity type is P-type, the first region is formed in a secondregion that is deeply diffused in the semiconductor substrate, thesecond region is of the N-type, and the semiconductor substrate isP-type, and further comprising: erasing a selected row of the memorycells by grounding the wordline overlying the selected row whileapplying a high positive voltage to the first region, the second region,and to the wordline overlying each deselected said row.
 33. The methodof claim 30, wherein during said writing, each deselected said wordlineis coupled to a positive voltage that is less than approximately half ofthe voltage applied to the selected wordline.
 34. A method of forming atransistor comprising: forming two parallel trenches in a first regionof a semiconductor substrate, said first region having a firstconductivity type, wherein each trench has a sidewall that faces thesidewall of the other trench, with a portion of the first region betweenthe facing sidewalls; implanting ions of a second conductivity type inthe facing sidewalls of the first and second trenches, whereby a sourceregion of the transistor is formed in the sidewall of one said trench, adrain region of the transistor is formed in the sidewall of the othersaid trench, a channel region of the transistor is in the first regionbetween the source and drain regions.
 35. The method of claim 34,further comprising filling the two trenches with a dielectric materialafter said implanting
 36. The method of claim 35, further comprisingforming a conductive gate of the transistor over the channel region. 37.The method of claim 34, further comprising forming a conductive gate ofthe transistor over the channel region.
 38. An integrated circuitcomprising: a semiconductor substrate including a first region of afirst conductivity type; parallel first and second trenches in the firstregion, the first and second trenches each having a sidewall, with thesidewall of the first trench facing the sidewall of the second trench; atransistor comprising a source region of a second conductivity typeimplanted in the sidewall of the first trench, and a drain region of thesecond conductivity type implanted in the facing sidewall of the secondtrench, wherein a portion of the first region between source and thedrain regions comprises a channel region of the transistor; a gate overthe channel region; and a dielectric material filling the first and thesecond trenches.
 39. The integrated circuit of claim 38, furthercomprising a plurality of the transistors, wherein the source regions ofthe transistors are part of a continuous line of a dopant of the secondconductivity type in the sidewall of the first trench, and the drainregions of the plural transistors are part of a continuous line of thedopant in the sidewall of the second trench.
 40. The integrated circuitof claim 39, wherein each said transistor comprises a nonvolatile memorycell.
 41. The integrated circuit of claim 38, wherein a plurality of thetransistors are formed between the facing sidewalls first and secondtrenches.
 42. The integrated circuit of claim 41, wherein the sourceregions of the plurality of transistors are respective subportions of asingle implant region, and the drain regions of the plurality oftransistors are respective subportions of a single implant region. 43.The integrated circuit of claim 39, wherein the gate comprises afloating gate overlaid by a control gate, wherein in the control gate isa subportion of a wordline that extends over dielectric material in thetrench.
 44. An integrated circuit comprising: a semiconductor substrateincluding a first region of a first conductivity type; a pair ofparallel implant region lines of a second conductivity type in the firstregion; a pair of field oxide region lines parallel to the implantregion lines, wherein a bird's beak region of one of the field oxideregion lines of the pair faces a bird's beak region of the other filedoxide region line of the pair, with the pair of implant region linesbeing within the par of field oxide region lines; and a plurality oftransistors formed between the pair of field oxide region lines, whereineach said transistor includes a source region that is a subportion ofone of the implant region lines and a drain region that is a subportionof the other implant region line, and a gate overlying a surface of thefirst region.
 45. The integrated circuit of claim 44, wherein the gatecomprises a floating gate and a control gate.
 46. The integrated circuitof claim 45, wherein the control gate is a subportion of a wordline thatextends over the pair of field oxide region lines.
 47. A non-volatilememory, comprising: a plurality of non-volatile memory cells in a row ina first region of a semiconductor substrate, wherein each said memorycell has a source region, a drain region, a channel-region between thesource and drain regions, and a floating gate; one or more dielectricisolation regions, wherein one of the isolation regions is betweenadjacent memory cells of the row; a polysilicon layer extendingintegrally over the plurality of the memory cells of the row and overeach said intervening dielectric isolation region, wherein an integralsubportion of the polysilicon layer over each of the respective memorycells forms a control gate for the memory cell.
 48. The non-volatilememory of claim 47, further comprising a plurality of the rows of thememory cells, arranged so the memory cells of the plurality of rows formcolumns of the memory cells, with each row having a separate overlyingone of the polysilicon layers.
 49. The non-volatile memory of claim 48,wherein the source regions of each memory cell of each said column ofthe memory cells are respective subportions of a contiguous firstimplant region line in the first region, the drain regions of eachmemory cell of each said column are respective subportions of acontiguous second implant region line in the first region, said secondimplant region line being parallel to the first implant region line. 50.An integrated circuit comprising: a first region of a first conductivitytype in a semiconductor substrate; parallel first and second implantregion lines of a second conductivity type in the first region; aplurality of conductive first gates overlying a surface of the firstregion between the first and second implant region lines, wherein eachsaid first gate is part of one of a plurality of transistors overlappingthe first and second implant region lines, with each said transistorincluding a subportion of the first implant line as a source region, asubportion of the second implant line as a drain region, and asubportion of the first region between the source and drain regions as achannel region.
 51. The integrated circuit of claim 50, wherein eachsaid transistor is a non-volatile memory cell.
 52. The integratedcircuit of claim 50, wherein the first gate is a floating gate, andfurther comprising a control gate over the first gate.